SiFive is seeing growing adoption, with more than two billion SiFive RISC-V-based chips already in the market.
SiFive, Inc. the gold standard for RISC-V computing, unveiled a major upgrade of its SiFive Essential product family at the RISC-V Summit Europe 2024. Developed over a decade, the field-proven Essential IP is already in use in billions of products including mobile phones, sensors, SSDs, FPGA platforms, surveillance cameras, smartwatches, and more.
This full-portfolio refresh brings higher performance, improved power efficiency, and more flexible interfaces, with configuration and integration options to cover virtually any possibility. The SiFive Essential Gen4 products are available on June 25.
"The best RISC-V embedded solutions just got much better with this fourth generation," said John Ronco, SiFive SVP of Product. "With the benefits of cost-effective flexibility, performance, and low power, RISC-V has won the battle for embedded. As legacy ISAs have reduced R&D and support, we are expanding SiFive's broad portfolio of market-leading Essential products and reaffirming our commitment and support for customers in these critical areas of innovation."
SiFive has seen strong momentum across embedded segments where the Essential Gen4 products will bring impressive flexibility and features to enable customers to better tailor their designs. More than two billion SiFive RISC-V-based chips for embedded devices have shipped to date, and the market continues to grow rapidly.
"The embedded space in 2024 represents a huge ($257 billion) market opportunity, growing with an 8.3% CAGR through 2030. RISC-V and SiFive have been increasingly gaining momentum and taking share from the other ISAs. SiFive is launching the products that these customers need while also innovating at the high performance and advanced AI levels," said Rich Wawrzyniak, Principal Analyst at The SHD Group. "It is a mistake to discount the importance of embedded products as the flexibility and software portability of RISC-V makes designing products with multiple cores—including the highest performance cores—easier, creating a clear pathway for RISC-V into the next generations of high-performance chips."
Essential Gen4 IP Portfolio Features:
The Essential Gen4 IP Portfolio offers the most comprehensive RISC-V CPU and system IP portfolio, featuring up to 40% runtime power reduction. It includes eight different baseline embedded cores, both 32-bit and 64-bit, ranging from 2-stage single-issue to 8-stage superscalar designs.
The portfolio boasts an improved L2 cache, enhanced L1 memory, extensive configuration and integration options, on-chip memory selection, advanced power management, security features, and support for system, peripheral, and front ports. It also includes robust debug and trace capabilities and leading software support, including embedded Linux, FreeRTOS, and Eclipse C/C++ IDE.
Essential Gen4 portfolio:
2-3 stage single issue (lowest power & area) | 8-stage single issue (Performance efficiency) | 8-stage dual issue (High performance) | |
64-bit app processors | U6 Gen 4 | U7 Gen 4 | |
64-bit real-time Embedded processors | S2 Gen 4 | S6 Gen 4 | S7 Gen 4 |
32-bit real-time Embedded processors | E2 Gen 4 | E6 Gen 4 | E7 Gen 4 |
Source: SiFive
Learn more about the SiFive Essential product family here.